method of managing interruption requests in a computational environment

专利摘要:
INTERRUPTION REQUIREMENTS MANAGEMENT METHOD IN A COMPUTATIONAL ENVIRONMENT One or more message signaled interruption requirements from one or more input / output (I / O) adapters are converted to I / O adapter event notifications. Each I / O adapter event notification includes the configuration of one or more specific indicators in system memory and an interrupt request, the first which results in a pending I / O adapter interruption requirement. While a requirement for an I / O adapter outage is pending, subsequent message-flagged outage requirements are converted to I / O adapter event notifications, but do not result in additional requirements for I / O adapter outages .
公开号:BR112012033821B1
申请号:R112012033821-8
申请日:2010-11-08
公开日:2020-11-03
发明作者:Eric Norman Lais；Gustav Sittmann Iii；David Craddock；Thomas Gregg；Mark Farrell；Janet Easton
申请人:International Business Machines Corporation.；
IPC主号:

专利说明:

[0001] This invention relates, in general, to the interrupt processing within a computational environment, and in particular, the manipulation of interrupts generated by the adapters of the computational environment.
[0002] Message-flagged interruption (MSI) is a way for an adapter function, such as a Peripheral Component Interconnect (PCI) function, to generate a central processing unit (CPU) interrupt to notify the operating system the occurrence of an event or the presence of some state. MSI is an alternative to having a dedicated interrupt pin on each device. When an adapter function is configured to use MSI, the function requests an interrupt by performing an MSI write operation from a specific number of data bytes to a special address. The combination of this special address and a unique data value is called an MSI vector.
[0003] Some adapter functions support only one MSI vector; other adapter functions support multiple MSI vectors. For functions that support multiple MSI vectors, the same special address is used with different data values.
[0004] On many computing platforms, a device driver configures itself as the interrupt handler associated with an MSI vector. This effectively associates an MSI vector with an input to a CPU interrupt vector. Therefore, when an adapter function supports multiple MSI vectors and is configured to use multiple MSI vectors, it consumes a corresponding number of entries in the CPU interrupt vector.
[0005] US publication No. 2007/0271559 Al, published November 22, 2007, Easton et al, "Virtualization of Infiniband Host Channel Adapter Interruptions", describes a method, system, program product and data structure of computer to provide two levels of server virtualization. A first hypervisor allows multiple logical partitions to share a set of resources and provides a first level of virtualization. A second hypervisor allows multiple independent virtual machines to share resources that are assigned to a single logical partition and provides a second level of virtualization. All events for all virtual machines within said single logical partition are grouped into a single partition-owned event queue to receive event notifications from the resources shared for that single logical partition. A requirement for an outage is signaled for events grouped from the partition-owned event queue for demultiplexing events grouped by the machine from the partition-owned event queue into individual virtualized event queues that are allocated on a per-machine basis.
[0006] US publication No. 2005/0289271 Al, published December 29, 2005, Martinez, et al, "Circuitry to Selectively Produce MSI Signals", describes, in some embodiments, the inventions include a chip having a circuit status record coupled with conductors to receive interrupt event signals to provide source signals corresponding to the interrupt event signals. The chip also includes a control register circuit to provide source enable signals for some selective interruption sources, and a logic reset circuit coupled with the conductors to receive the interrupt event signals and provide a reset signal. The chip additionally includes the first logic circuit to receive the source signals, the source enable signals, and the reset signal to provide an initial interrupt signal, and message interrupted signal pulse generation (MSI) logic. ) to receive the initial interrupt signal and provide an MSI signal in response to it. Other embodiments are described and claimed.
[0007] U.S. Patent No. 7,562,366, issued on July 14, 2009, by Pope et al, "Transmit Completion Event Batching", describes a method for managing a data transmission queue, for use with a host and a network interface device. Generally described, the host writes data staging descriptors to a transmission descriptor queue, and the network interface device writes events to notify the host when it has completed processing a transmission data staging. Each of the transmission completion event descriptors notifies the host of the completion of a plurality of transmission data temporary stores. Brief Summary
[0008] In accordance with an aspect of the present invention, a capability is provided to facilitate the management of interrupt requirements from the adapters.
[0009] The disadvantages of the prior art are overcome and advantages are provided through the provision of a method according to claim 1, and the corresponding computer program system and product for managing interruption requirements in a computational environment. Brief Description of the Various Views of the Drawings
[0010] One or more aspects of the present invention are particularly pointed out and distinctly claimed as examples in the claims at the conclusion of the specification. The previous objectives and other objectives, functionalities, and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which: Figure 1 represents an embodiment of a computational environment to incorporate and use one or more aspects of the present invention; Figure 2 represents an embodiment of additional details of the system memory and the I / O hub of Figure 1, in accordance with an aspect of the present invention; Figures 3A-3B represent examples of adapter interrupt bit vector allocations, in accordance with an aspect of the present invention; Figures 3C-3D represent examples of adapter interrupt summary bit allocations, in accordance with an aspect of the present invention; Figure 4 represents an embodiment of an overview of the logic to be performed during initialization to configure an adapter function for I / O adapter event notification, in accordance with an aspect of the present invention; Figure 5 represents an embodiment of the logic to perform the registration to allow the conversion of a message signaled interrupt (MSI) into an I / O adapter event notification, in accordance with an aspect of the present invention; Figure 6A represents an embodiment of the logic for converting an MSI requirement to an I / O adapter event notification, in accordance with an aspect of the present invention; Figure 6B represents an embodiment of the logic for presenting the I / O adapter event notification for an operating system, in accordance with an aspect of the present invention; Figure 7A represents an embodiment of a Modification PCI Function Controls instruction used in accordance with an aspect of the present invention; Figure 7B represents an embodiment of a field used by the Modification PCI Function Controls instruction of figure 7A, in accordance with an aspect of the present invention; Figure 7C represents an embodiment of another field used by the Modification PCI Function Controls instruction of figure 7A, in accordance with an aspect of the present invention; Figure 7D represents an embodiment of the contents of a function information block (FIB) used in accordance with an aspect of the present invention; Figure 8 represents an embodiment of an overview of the logic of the Modification PCI Function Controls instruction, in accordance with an aspect of the present invention; Figure 9 represents an embodiment of the logic associated with a registration adapter interrupt operation that can be specified by the Modification PCI Function Controls instruction, in accordance with an aspect of the present invention; Figure 10 represents an embodiment of the logic associated with an unregister adapter interruption operation that can be specified by the Modification PCI Function Controls instruction, in accordance with an aspect of the present invention; Fig. 11A represents an embodiment of a Logic Call Processor instruction used in accordance with an aspect of the present invention; Figure 11B represents an embodiment of a requirement block used by the Call Logic Processor instruction of figure 11A for a list operation, in accordance with an aspect of the present invention; Figure 11C represents an embodiment of a response block for the list operation of Figure 11B, according to an aspect of the present invention; Figure 11D represents an embodiment of a function list entry used in accordance with an aspect of the present invention; Figure 12A represents an embodiment of a requirement block used by the Call Logic Processor instruction of figure 11A for a request function operation, in accordance with an aspect of the present invention; Figure 12B represents an embodiment of a response block for the operation of the request function of Figure 12A, according to an aspect of the present invention; Figure 13A represents an embodiment of a requirement block used by the Call Logic Processor instruction of figure 11A for a group request operation, in accordance with an aspect of the present invention; Figure 13B represents an embodiment of a response block for the request group operation of Figure 13A, in accordance with an aspect of the present invention; Figure 14 represents an embodiment of a computer program product that incorporates one or more aspects of the present invention; Figure 15 represents an embodiment of a host computer system for incorporating and using one or more aspects of the present invention; Figure 16 represents a further example of a computer system for incorporating and using one or more aspects of the present invention; Figure 17 represents another example of a computer system comprising a computer network for incorporating and using one or more aspects of the present invention; Figure 18 represents an embodiment of various elements of a computer system to incorporate and use one or more aspects of the present invention; Figure 19A represents an embodiment of the execution unit of the computer system of Figure 18 to incorporate and use one or more aspects of the present invention; Figure 19B represents an embodiment of the branching unit of the computer system of Figure 18 to incorporate and use one or more aspects of the present invention; Figure 19C represents an embodiment of the loading / storage unit of the computer system of Figure 18 to incorporate and use one or more aspects of the present invention; and Figure 20 represents an embodiment of an emulated host computer system to incorporate and use one or more aspects of the present invention. Detailed Description
[0011] In accordance with an aspect of the present invention, an ability is provided to convert the message signaled interrupt (MSI) requirement to an input / output adapter (I / O) event notification. The MSI is requested by an adapter and converted to an adapter event notification, in which one or more specific indicators are defined and a requirement is made that an interrupt is presented to an operating system (or other software, such as other programs) , etc. As used here, the term operating system includes operating system device drivers). In a particular example, each MSI requirement does not result in an interruption requirement for the operating system, but instead, an interruption requirement encompasses a plurality of MSI requirements.
[0012] As used here, the term "adapter" includes any type of adapter (for example, storage adapter, network adapter, processing adapter, cryptographic adapter, PCI adapter, other type of input / output adapter, etc. .). In one embodiment, an adapter includes an adapter function. However, in other embodiments, an adapter can include a plurality of adapter functions. One or more aspects of the present invention are applicable if an adapter includes an adapter function or a plurality of adapter functions. In addition, in the examples presented here, the adapter is used interchangeably with the adapter function (for example, PCI function) unless otherwise noted.
[0013] An embodiment of a computational environment to incorporate and use one or more aspects of the present invention is described with reference to figure 1. In one example, a computational environment 100 is a System z® server offered by International Business Machines Corporation. System z® is based on z / Architecture® offered by International Business Machines Corporation. Details regarding az / Architecture® are described in an IBM® publication titled, “z / Architecture Principles of Operation”, IBM Publication No. SA22-7832-07, February 2009. IBM®, System z® ez / Architecture® are registered trademarks of International Business Machines Corporation, Armonk, New York. Other names used here may be registered trademarks, trademarks or product names of International Business Machines Corporation or other companies.
[0014] In one example, computing environment 100 includes one or more central processing units (CPUs) 102 coupled with system memory 104 (also known as main memory) through a memory controller 106. To access system memory 104, a central processing unit 102 issues a read or write requirement that includes an address used to access system memory. The address included in the requirement is typically not directly useful for accessing system memory, and therefore is translated into an address that is directly usable for accessing system memory. The address is translated using a translation mechanism (XLATE) 108. For example, the address is translated from a virtual address to a real or absolute address using, for example, dynamic address translation (DAT).
[0015] The requirement, including the address (translated, if necessary), is received by memory controller 106. In one example, memory controller 106 is comprised of hardware and is used to arbitrate for access to system memory and to maintain consistency of memory. This arbitration is performed for requirements received from CPUs 102, as well as for requirements received from one or more adapters 110. Like central processing units, adapters issue requirements to system memory 104 to gain access to the system memory.
[0016] In one example, adapter 110 is a Peripheral Component Interconnect (PCI) or PCI Express (PCTe) adapter that includes one or more PCI functions. The PCI function issues a requirement that is routed to an input / output hub 112 (for example, a PCI hub) through one or more switches (for example, PCIe Switches) 114. In one example, the input / output is comprised of hardware, including one or more state machines.
[0017] The input / output hub includes, for example, a root complex 116 that receives the requirement from a switch. The requirement includes an input / output address that is used to perform a direct memory access (DMA) or to request an interrupt signaled by message (MSI), as examples. This address is provided for an address translation and protection unit 118 that accesses the information used for any of the DMA or MSI requirements.
[0018] For a DMA operation, the address protection and translation unit 118 can translate the address into an address usable for accessing system memory. Then, the requirement initiated from the adapter, including the translated address, is provided for memory controller 106 through, for example, an I / O bus for memory 120. The memory controller performs its arbitration and directs the requirement with the address translated into system memory at the appropriate time.
[0019] For an MSI requirement, information in the address translation and protection unit 118 is obtained to facilitate the conversion of the MSI requirement to an I / O adapter event notification. Since the embodiments described here refer to interrupt processing, additional details regarding the I / O hub and system memory as they refer to interrupt processing are described with reference to figure 2. In figure 2, the memory controller is not shown, but can be used. The I / O hub can be coupled with system memory 104 and / or processor 254 directly or via a memory controller.
[0020] Referring to Figure 2, in one example, system memory 104 includes one or more data structures usable in facilitating interrupt processing. In this example, system memory 104 includes an adapter interrupt bit vector (AIBV) 200 and an optional adapter interrupt summary (AISB) bit 202 associated with a particular adapter. There can be an AIBV and a corresponding AISB for each adapter.
[0021] In one example, the adapter interrupt bit vector 200 is a single-dimensional arrangement of one or more bits in main storage that are associated with an adapter (for example, the PCI function). The bits in the adapter interrupt bit vector represent the MSI vector numbers. A bit that is set to one in an AIBV indicates a condition or event type for the associated adapter. In the PCI function example, each bit in the associated AIBV corresponds to an MSI vector. Therefore, if the PCI function supports only one MSI vector, its AIBV includes a single bit; if the PCI function supports multiple MSI vectors, your AIBV includes one bit per MSI vector. In the example shown in Figure 2, the PCI function supports multiple MSI vectors (for example, 3), and therefore there are multiple bits (for example, 3) in AIBV 200. Each bit corresponds to a particular event, for example , bit 0 of AIBV, when set to one, indicates a completed operation; bit 1 of AIBV, when set to one, corresponds with an error event; etc. As shown, bit 1 is set in this example.
[0022] In a particular example, a command (for example, a Modify PCI function Controls command) is used to assign an AIBV to the PCI function. Specifically, the command is issued by the operating system and specifies the identity of the PCI function, the main storage location of the area that includes AIBV, the offset from that location to the first bit of AIBV, and the number of bits that comprise the AIBV. In particular, using this command, adapter interrupt parameters are copied from a function information block that stores such information (for example, obtained from initialization and / or configuration) to the adapter's device table entry. (described below) and / or the function table entry (described below).
[0023] The PCI function identity, in one example, is a function identifier. A role identifier includes, for example, an enabling indicator that indicates whether the PCI role enabling is enabled; the PCI function number that identifies the function (this is a static identifier); and a case number that indicates the particular case of this role identifier. For example, each time the function identifier is enabled, the case number is increased to provide a new case number. The role identifier is used to find a role table entry in a role table that includes one or more entries. For example, one or more bits of the function identifier are used as an index to the function table to locate the particular function table entry. The function table entry includes information regarding its associated PCI function. For example, it can include several indicators that refer to the state of its associated adapter role, and it can include one or more device table entry indexes used to find device table entries for this adapter role (for the operating system, in one embodiment, the identifier is simply an opaque identifier for the adapter).
[0024] An AIBV can be allocated any byte limit and any bit limit. This allows the operating system the flexibility to package AIBVs from multiple adapters to a contiguous range of bits and bytes. For example, as shown in figure 3A, in one example, the operating system has designated a common storage area at location X to include five contiguous AIBVs. The adapter associated with each AIBV is identified by the letters A-E. The event that each AIBV bit represents for an adapter is additionally identified by the numbers 0-n. Unsigned bits are identified by the lowercase letter "u".
[0025] An additional example is shown in figure 3B. In this example, the operating system has designated three unique storage areas, at locations X, Y, and Z to include AIBVs for five I / O adapters. Storage at location X includes AIBVs for adapters A and B, storage at location Y includes AIBV for adapter C only, and storage at location Z includes AIBVs for adapters D and E. The event where each AIBV bit represents an I / O adapter that is additionally identified by the numbers 0-n. The unsigned bits are identified by the letter "u".
[0026] Returning to figure 2, in addition to AIBV, in this example, there is an AISB 202 for the adapter, which includes a single bit associated with the adapter. An AISB that is one that indicates that one or more bits have been set to one in an AIBV associated with the AISB. AISB is optional, and there can be one for each adapter, one for each selected adapter or one for a group of adapters.
[0027] In a particular implementation for PCI functions, a command (for example, a Modify PCI function Controls command) is used to designate an AISB for the PCI function. Specifically, the command is issued by the operating system and specifies the identity of the PCI function (for example, the identifier), the main storage location of the area that includes AISB, the move from that location to AISB, and a control adapter interrupt summary notification enabling whether a summary bit exists.
[0028] An AISB can be allocated in any byte limit and any bit limit. This allows the operating system the flexibility to package AISBs from multiple adapters to a contiguous range of bits and bytes. In one example, as shown in Figure 3C, the operating system has designated a common storage area, at location X, to include nine contiguous AISBs. The adapter associated with each AISB is identified by the letters A-I. Unsigned bits are identified by the lowercase letter "u".
[0029] An example of additional allocation is shown in figure 3D, where the operating system has designated three unique AISB storage locations, at locations X, Y and Z to include the AISBs for each of the three adapters. The adapters associated with each AISB are identified with the letters A-C. Unsigned bits are identified by the lowercase letter "u".
[0030] Additionally, the program can also designate a single AISB for multiple PCI functions. This associates multiple AIBVs with a single summary bit. Therefore, such an AISB is one that indicates that the operating system must scan multiple AIBVs.
[0031] Returning to figure 2, in an example, AIBV and AISB are highlighted by the addresses located in a device table entry 206 of a device table 208 located in I / O hub 112. In one example, the Device table 208 is located inside the I / O hub's address translation protection unit.
[0032] Device table 208 includes one or more entries 206, each of which is designated for a particular adapter function 210. A device table entry 206 includes a number of fields, which can be populated using, for example , the commands mentioned above. The values of one or more of the fields are based on the policy and / or the configuration. Examples of the fields include: Interrupt Subclass (ISO) 214: Indicates an interrupt subclass for the interrupt. The ISO identifies a maskable class of adapter interrupts that can be associated with a priority with which the operating system will process the interrupt; AIBV address (@) 216: Provides, for example, an absolute address from the beginning of the storage location that includes AIBV for the particular adapter role assigned to this device table entry; AIBV 218 offset: An offset to the main storage location for the start of the AIBV; AISB address (@) 220: Provides, for example, an absolute address from the beginning of the storage location that includes AISB for this PCI function, if the operating system has designated an AISB; AISB 222 offset: An offset to the main storage location for AISB; Adapter interrupt summary notification enable control (Enabled) 224: This control indicates whether an AISB exists; Number of Interruptions (NOI) 226: Indicates the maximum number of MSI vectors allowed for this PCI function, with zero indicating that none are allowed.
[0033] In other embodiments, the DTE may include more, less or different information.
[0034] In one embodiment, the device table entry to be used for a particular interruption requirement by an adapter is located using, for example, a requester identifier (RID) (and / or a portion of the address) located at a requirement issued by the adapter (for example, PCI 210 function). The requirement ID (for example, a 16-bit value specifying, for example, a bus number, device number and function number) is included in the requirement, as well as an address to be used for the interrupt. The requirement, including the RID and the address, is provided for, for example, an addressable content memory (CAM 230) via, for example, a switch, and the addressable content memory is used to provide an index value. For example, the CAM includes multiple entries, with each entry corresponding to an index for the device table. Each CAM entry includes the value of a RID. If, for example, the received RID matches the value contained in an entry in the CAM, the corresponding device table index is used to locate the device table entry. That is, the output from the CAM is used to index to the device table 208. If there is no match, the received packet is discarded. (In other embodiments, the CAM or other observation is not required and the RID is used as the index.) The localized DTE is used in the processing of an interrupt request, as described here.
[0035] To request an interrupt, adapter function 210 sends a packet to the I / O hub. This packet has an MSI address 232 and associated data 234. The I / O hub compares at least part of the received address with a value in an MSI 250 comparison record. If there is a match, then an interruption (for example , MSI) is being requested, as opposed to a DMA operation. The reason why the requirement (ie, type of event that occurred) is indicated in the associated data 234. For example, one or more of the low-order bits of data are used to specify a particular interrupt vector (that is, a vector MSI) indicating the reason (event).
[0036] In accordance with an aspect of the present invention, an interrupt request received from the adapter is converted to an I / O adapter event notification. That is, one or more indicators (for example, one or more AIBVs and optionally an AISB) are defined and an interruption to the operating system is requested, if one is not already pending. In one embodiment, multiple interrupt requirements (for example, MSIs) from one or more adapters are coalesced into a single interrupt for the operating system, but with respective AIBV and AISB indications. For example, if the I / O hub has already received an MSI requirement, it in turn has already provided an interrupt request for a processor, and this interruption is still pending (for example, for one reason or another, the interruption has not yet was presented to the operating system (for example, interrupts are disabled), so if the hub receives one or more other MSIs, it does not request additional interruptions. An interrupt replaces and represents the plurality of MSI requirements. However, one or more AIBVs and optionally one or more AISBs are defined.
[0037] Additional details regarding the conversion of an MSI (or other adapter interruption requirement) to an I / O adapter event notification are described below with reference to figures 4-6B. In particular, figure 4 describes several initializations to be carried out; figure 5 describes a registration process; Figure 6A describes logic for converting an MSI to an adapter event notification; and figure 6B describes logic for presenting the I / O adapter event notification for the operating system.
[0038] Referring to figure 4, in an example, to convert an MSI requirement to an I / O adapter event notification a certain initialization is performed. During startup, the operating system performs a number of steps to configure an adapter for adapter event notification via an MSI requirement. In this example, it is the PCI function being configured; although, in other embodiments, it may be from other adapters, including other types of adapter functions.
[0039] Initially, in one embodiment, a determination is made as if the PCI functions in the configuration, STEP 400. In one example, a command (for example, a Request List command) issued by the operating system is used to obtain a list of the PCI functions assigned to the requirement configuration (for example, designated for a particular operating system). This information is obtained from a configuration data structure that maintains this information.
[0040] Next one of the PCI functions in the list is selected, STEP 402, and a determination is made as if for an MSI address to be used for the PCI function and the number of MSI vectors supported by the PCI function . An MSI address is determined based on the characteristics of the I / O hub and the system on which it is installed. The number of MSI vectors supported is based on the policy and is configurable.
[0041] Additionally, AIBV is allocated, as well as AISB, if any, STEP 410. In one example, the operating system determines the location of AIBV to allow efficient processing of one or more adapters, typically based on class adapter. For example, AIBVs for storage adapters can be located adjacent to each other. AIBV and AISB are allocated and released to zeroes, and a record adapter interrupt operation is specified (for example, using a Modify PCI Function Controls statement). This operation records the AIBV, the AISB, the ISC, the number of interruptions (MSI Vectors), and the adapter interrupt summary notification enable control, as described in additional detail below, STEP 412. Next, the configuration space of the PCI function is read / written, STEP 414. Specifically, an MSI address and MSI vector count are written consistent with the previous record.
[0042] Next, a determination is made as to whether there are additional functions in the list, CONSULTATION 416. If so, processing continues with STEP 402. Otherwise, initialization processing is complete.
[0043] Additional details regarding the registration of various parameters are described with reference to figure 5. Initially, the device table entry (DTE) to correspond with the PCI function for which initialization is being performed is selected. This selection is made, for example, through the management firmware that selects an available DTE from the device table. Next, the various parameters are stored in the device table entry, STEP 502. For example, ISC, AIBV address, AIBV offset, AISB address, AISB offset, enabling control, and the number of interruptions (NOI) are set to values obtained from the function configuration. This completes the registration process.
[0044] As used here, firmware includes, for example, the microcode, milicode and / or macrocode of the processor. It includes, for example, the hardware level instructions and / or data structures used in the implementation of higher level machine code. In one embodiment, it includes, for example, proprietary code that is typically distributed as microcode that includes reliable software or microcode specific to the underlying hardware and controls operating system access to the system hardware.
[0045] During operation, when the PCI function wants to generate an MSI, it typically makes some information available to the operating system that describes the condition. This causes one or more steps to occur in order to convert the MSI requirement of the PCI function to an I / O adapter event notification for the operating system. This is described with reference to figure 6A.
[0046] With reference to figure 6A, initially, a description of the event for which the interruption is requested is recorded, STEP 600. For example, the PCI function records a description of the event in one or more recording structures of description of adapter-specific events stored, for example, in system memory. This may include recording the type of event, as well as recording additional information. Additionally, a requirement is initiated by the PCI function specifying an MSI address and the MSI vector number, as well as a requirement ID, STEP 601. This requirement is received by the I / O hub, and responsive to responding to the requirement , the requirement ID in the requirement is used to locate the device table entry for the PCI function, STEP 602. The I / O hub compares at least a portion of the address in the requirement with the value in a comparison record. MSI, CONSULTATION 603. If they are unequal, an MSI is not being requested. However, if they are the same, then an MSI address was specified, and thus an MSI was requested, rather than a direct memory access operation.
[0047] Next, a determination is made as to whether the number of MSI vectors specified in the requirement is less than or equal to the number of interrupts (NOI) allowed for this function, CONSULT 604. If the number of MSI vectors is greater than NOI, an error is indicated. Otherwise, the I / O hub issues an adjustment bit function to adjust the appropriate AIBV bit in the storage. The appropriate bit is determined by adding the MSI vector number for the AIBV Offset specified in the device table entry and shifting this number of bits from the AIBV Address specified in the device table entry, STEP 605. In addition, if an AISB has been designated, the I / O hub uses an adjustment bit function to adjust the AISB, using the AISB Address and AISB Offset in the device table entry, STEP 606.
[0048] Next in an embodiment, a determination is made (for example, by the CPU or the I / O hub) as to whether an interrupt request is already pending. To make this determination, a pending indicator is used. For example, a pending indicator 252 (figure 2) stored in the memory of a processor 254, which is accessible to processors in the computing environment that can process the interrupt (for example, CPUs 102 in figure 1), is checked, CONSULTATION 608. If it is not defined, then it is defined (for example, to 1), STEP 610. If it is already defined, processing is complete and another interruption requirement is not required. Therefore, subsequent interruption requirements are encompassed by the only pending requirement.
[0049] In a particular example, there may be one pending indicator per Interruption Subclass, and therefore the pending indicator of the interruption subclass designated for the ordering function is the indicator that is verified.
[0050] Asynchronously, as shown in figure 6B, one or more processors check the pending indicator, CONSULT 640. In particular, each processor enabled for ISC polls (and the zone in another embodiment) in the indicator for ISC when , for example, interrupts are enabled for that processor (that is, for its operating system). If one of the processors determines that the indicator is set, it arbitrates with the other processors enabled for the same ISC (and zone in another embodiment) to present the interruption, STEP 642. Returning to CONSULTATION 640, if the pending indicator is not defined , ISC-enabled processors continue to vote for a defined indicator.
[0051] In response to the operating system that is presented with the interruption, STEP 642, the operating system determines whether there are any AISBs are registered, CONSULT 643. If not, the operating system processes the defined AIBVs, as described below, STEP 645 Otherwise, the operating system processes any defined AISBs and AIBVs, STEPS 644, 645. For example, it checks whether any AISBs are defined. If so, it uses AISB to determine the location of one or more AIBVs. For example, the operating system remembers the locations of AISBs and AIBVs. Additionally, remember which adapter each AISB and AIBV represents. Therefore, it can maintain a form of a control block or other data structure that includes the locations of AISBs and AIBVs and the association between AISBs, AIBVs and adapter ID. It uses this control block to facilitate finding an AIBV based on its associated AISB. In an additional embodiment, an AISB is not used. In this situation, the control block is used to locate the particular AIBV.
[0052] In response to the location of one or more AIBVs, the operating system scans the AIBVs and processes any defined AIBVs. It processes the interrupt in a manner consistent with the event presented (for example, it provides the state). For example, with a storage adapter, an event can indicate that an operation has been completed. This results in the operating system checking the state stored by the adapter to see if the operation completed successfully and also details of the operation. In the case of a storage readout, this is an indication that the data read from the adapter is now available in the system memory and can be processed.
[0053] In one embodiment, if during the conversion operation, an error is detected, an attention is generated for the system firmware, instead of converting the MSI requirement to an adapter event notification.
[0054] Additional details regarding the Modification PCI Function Controls instruction used to record adapter interrupts are described here. Referring to figure 7A, a Modification PCI Function Controls instruction 700 includes, for example, an opcode (operation code) 702 indicating the Modification PCI Function Controls instruction; a first field 704 specifying a location where varied information is included with respect to the adapter function for which the operational parameters are being established; and a second field 706 specifying a location from which the PCI function information block (FIB) is fetched. The contents of the locations designated by Fields 1 and 2 are further described below.
[0055] In one embodiment, Field 1 designates a general record that includes varied information. As shown in figure 7B, the contents of the registry include, for example, a function identifier 710 that identifies the identifier of the adapter function on behalf of which the modify instruction is being performed; an address space 712 designating an address space in the system memory associated with the adapter role designated by the role identifier; an operation control 714 that specifies the operation to be performed for the adapter function; and state 716 which provides status with respect to the instruction when the instruction completes with a predefined code.
[0056] In one embodiment, the function identifier includes, for example, an enabling indicator indicating whether the identifier is enabled, a function number that identifies an adapter function (this is a static identifier and can be used to index in a function table); and a case number specifying the particular case for this role identifier. There is a role identifier for each adapter role, and it is used to find a role table (FTE) entry within the role table. Each function table entry includes operational parameters and / or other information associated with its adapter function. As an example, a function table entry includes: Case number: This field indicates a particular case of the adapter function identifier associated with the function table entry; device table entry index (DTE) l ... n: There can be one or more device table indexes, and each index is an index to a device table to find a device table entry (DTE). There are one or more device table entries per adapter role, and each entry includes information associated with your adapter role, including information used to process adapter role requirements (for example, DMA requirements, MSI requirements) and information regarding requirements associated with the adapter function (for example, PCI instructions). Each device table entry is associated with an address space within the system memory assigned to the adapter role. An adapter role can have one or more address spaces within the system memory assigned to the adapter role. Busy indicator: This field indicates whether the adapter function is busy; Permanent error status indicator: This field indicates whether the adapter function is in a permanent error state; Recovery initiated indicator: This field indicates whether recovery has started for the adapter role; Permission indicator: This field indicates whether the operating system trying to control the adapter role has the authority to do this; Enabling indicator: This field indicates whether the adapter function is enabled (for example, l = enabled, O = disabled); Requestor Identifier (RID): This is an adapter role identifier, and includes, for example, a bus number, a device number and a function number.
[0057] In one example, this field is used for accessing an adapter function configuration space. (An adapter's memory can be defined as address spaces, including, for example, a configuration space, an I / O space, and / or one or more memory space). In one example, the configuration space can be accessed by specifying the configuration space in an instruction issued by the operating system (or other configuration) for the adapter role. An offset to the configuration space and a function identifier used to locate the appropriate function table entry that includes the RID is specified in the instruction. The firmware receives the instruction and determines that it is for a configuration space. Therefore, it uses the RID to generate a requirement for the I / O hub, and the I / O hub creates a requirement to access the adapter. The location of the adapter role is based on the RID, and the offset specifies an offset to the adapter role configuration space.
[0058] Base address record (BAR) (1 an): This field includes a plurality of unsigned integers, designated as BARo - BARn, which are associated with the adapter function originally specified, and those in which they are also stored in the base address records associated with the adapter role. Each BAR specifies the starting address of a memory space or I / O space within the adapter function, and also indicates the type of address space, that is, whether it is a 64 or 32 bit memory space, or a 32-bit I / O space, like the examples.
[0059] In one example, it is used for access to memory space and / or I / O space of the adapter function. For example, an offset provided in an instruction to access the adapter function is added to the value in the base address register associated with the address space designated in the instruction to obtain the address to be used to access the adapter function. The address space identifier provided in the instruction identifies the address space within the adapter function to be accessed and the corresponding BAR to be used;
[0060] Size l .... n: This field includes a plurality of unsigned integers, designated as SIZEQ-SIZEn. The value of a Size field, when different from zero, represents the size of each address space with each entry corresponding to a BAR previously described.
[0061] Additional details regarding BAR and Size are described below. 1. When a BAR is not implemented for an adapter function, the BAR field and its corresponding size field are both stored as zeros. 2. When a BAR field represents either an I / O address space or a 32-bit memory address space, the corresponding size field is different from zero and represents the size of the address space. 3. When a BAR field represents a 64-bit memory address space, a. The BARn field represents the least significant address bits. B. The next consecutive BARn + i field represents the most significant address bits. ç. The corresponding SIZEn field is nonzero and represents the size of the address space. d. The corresponding SIZEn + í field is meaningless and is stored as zero.
[0062] Internal routing information: This information is used to perform particular routing for the adapter. It includes, for example, node, processor chip, and hub addressing information, as examples.
[0063] Status indication: This provides an indication of, for example, whether loading / storage operations are blocked or the adapter is in an error state, as well as other indications.
[0064] In one example, the busy indicator, the permanent error status indicator, and the indicator started by recovery are defined based on the monitoring performed by the firmware. Additionally, the permission indicator is defined, for example, based on the policy; and the BAR information is based on the configuration information discovered during a bus walk by the processor (for example, processor firmware). Other fields can be defined based on configuration, initialization and / or events. In other embodiments, the function table entry may include more, less or different information. The information included may depend on the operations supported by or enabled for the adapter function.
[0065] Referring to Figure 7C, in one example, Field 2 designates a logical address 720 of the PCI function information block (FIB), which includes information regarding an associated adapter function. The function information block is used to update a device table entry and / or function table entry (or other location) associated with the adapter role. The information is stored in FIB during the initialization and / or configuration of the adapter and / or in response to particular events.
[0066] Additional details regarding a function information block (FIB) are described with reference to figure 7D. In one embodiment, a function information block 750 includes the following fields: Format 751: This field specifies the format of the FIB. Interception Control 752: This field is used to indicate whether the guest execution of specific instructions by a guest in a pageable manner results in instruction interception; Error indication 754: This field includes the error indication status for direct memory access and adapter interrupts. When the bit is set (for example, 1), one or more errors were detected while direct access to memory or adapter interruption is performed for the adapter function; Blocked loading / storage 756: This field indicates whether loading / storage operations are blocked; Valid PCI function 758: This field includes an enabling control for the adapter function. When the bit is set (for example, 1), the adapter function is considered to be enabled for I / O operations; Registered Address Space 760: This field includes a control enabling direct memory access for an adapter function. When the field is defined (for example, 1) direct access to memory is enabled; Page size 761: This field indicates the size of the page or other memory unit to be accessed by a DMA memory access; PCI Base Address (PBA) 7 62: This field is a base address for an address space in the system memory designated for the adapter role. It represents the smallest virtual address that an adapter role is allowed to use for direct access to memory for the specified DMA address space; PCI Address Limit (PAL) 764: This field represents the largest virtual address that an adapter role is allowed to access within the specified DMA address space; Input / output address translation pointer (10 AT) 766: The input / output address translation pointer designates the first of any translation tables used by a PCI virtual address translation, or can directly designate the absolute address a storage frame that is the result of the translation; Interrupt Subclass (ISC) 768: This field includes the interrupt subclass used to present adapter interrupts for the adapter function; Number of Interruptions (NOI) 770: This field designates the number of distinct interrupt codes accepted by an adapter function. This field also defines the size, in bits, of the adapter interrupt bit vector designated by an adapter interrupt bit vector address and adapter interrupt bit vector offset fields; Adapter interrupt bit vector address (AIBV) 772: This field specifies an adapter interrupt bit vector address for the adapter function. This vector is used in interrupt processing; 774 adapter interrupt bit offset (offset): This field specifies the offset of the first adapter interrupt bit vector bit for the adapter function; Bit adapter interrupt summary (AISB) address 776: This field provides an address designating the adapter interrupt summary bit, which is optionally used in interrupt processing; Adapter interrupt summary bit offset 778: This field provides the offset for the adapter interrupt summary bit vector; Function Measurement Block Address (FMB) 780: This field provides an address of a function measurement block used to collect measurements with respect to the adapter function; Function Measurement Block Key 7 82: This field includes an access key to access the function measurement block; Summary Bit Notification Control 784: This field indicates whether there is a summary bit vector being used; Instruction Authorization Token 786: This field is used to determine whether a paged storage mode guest is authorized to execute PCI instructions without host intervention.
[0067] In one example, on z / Architecture®, a paged guest is executed interpretively through the Initial Interpretative Execution (SIE) instruction, at level 2 of interpretation. For example, the logical partition hypervisor (LPAR) executes the SIE instruction to start the logical partition in physical fixed memory. If z / VM® is the operating system on that logical partition, it issues the SIE instruction to run its guest (virtual) machines in its V = V (virtual) storage. Therefore, the LPAR hypervisor uses SIE level 1, and the z / VM® hypervisor uses SIE level 2; and Address Translation Format 787: This field indicates a selected format for address translation from the higher level translation table to be used in the translation (eg segment table, 3rd region, etc.).
[0068] The information information block designated in the Modification PCI Function Controls instruction is used to modify a selected device table entry, function table entry and / or other firmware controls associated with the adapter designated in the instruction. By modifying the device table entry, function table entry and / or other firmware controls, certain services are provided for the adapter. These services include, for example, adapter outages; address translations; error status reset; blocked loading / storage restarted; adjustment function measurement parameters; and adjustment interception control.
[0069] An embodiment of the logic associated with the Modification PCI Function Controls instruction is described with reference to figure 8. In one example, the instruction is issued by an operating system (or other configuration) and executed by the processor (for firmware) running the operating system. In the examples here, the adapter instruction and functions are based on PCI. However, in other examples, a different adapter architecture and corresponding instructions can be used.
[0070] In one example, the operating system provides the following operands for the instruction (for example, in one or more registers designated by the instruction): enabling the PCI function; the DMA address space identifier; an operation control; and an address of the function information block.
[0071] In reference to figure 8, initially, a determination is made as if the installation that allows for a Modification PCI Function Controls instruction is installed, CONSULT 800. This determination is made, for example, through the verification of an indicator stored, for example, in a control block. If the facility is not installed, an exception condition is provided, STEP 802. Otherwise, a determination is made as if the instruction was issued by a paged storage mode guest (or another guest), CONSULT 804. If yes, the host operating system will emulate the operation for this guest, STEP 806.
[0072] Otherwise, a determination is made as if one or more of the operands are aligned, CONSULT 808. For example, a determination is made as if the address of the function information block is on a double word limit. In one example, this is optional. If the operands are not aligned, then an exception condition is provided, STEP 810.
[0073] Otherwise, a determination is made as if the function information block is accessible, CONSULT 812. If not, then an exception condition is provided, STEP 814. Otherwise, a determination is made as if the identifier provided in the operands of the Modification PCI Function Controls instruction is enabled, CONSULT 816. In one example, this determination is made by checking an enabling indicator on the identifier. If the identifier is not enabled, then an exception condition is provided, STEP 818.
[0074] If the identifier is enabled, then the identifier is used to locate a function table entry, STEP 820. That is, at least a portion of the identifier is used as an index for the function table to locate the function table entry. function table corresponding to the adapter function for which the operating parameters are to be established.
[0075] A determination is made as to whether the function table entry was found, CONSULT 822. If not, then an exception condition is provided, STEP 824. Otherwise, if the configuration that issues the instruction is a guest, CONSULTATION 826, then an exception condition (for example, interception for the host) is provided, STEP 828. This request can be ignored if the configuration is not a guest or other authorizations can be verified, if assigned.
[0076] A determination is then made as if the function is enabled, CONSULTATION 830. In one example, this determination is made by checking an enabling indicator in the function table entry. If it is not enabled, then an exception condition is provided, STEP 832.
[0077] If the function is enabled, then a determination is made as to whether recovery is active, CONSULT 834. If recovery is active as determined by a recovery indicator in the function table entry, then an exception condition is provided, STEP 836. However, if recovery is not active, then an additional determination is made as to whether the function is busy, CONSULT 838. This determination is made by checking the busy indicator in the function table entry. If the function is busy, then a busy condition is provided, STEP 840. With the busy condition, the instruction can be tried again, instead of being left.
[0078] If the function is not occupied, then an additional determination is made as to whether the function information block format is valid, SEE 842. For example, the FIB format field is checked to determine whether this format is supported through the system. If it is invalid, then an exception condition is provided, STEP 844. If the function information block format is valid, then an additional determination is made as to whether the operation control specified in the instruction operands is valid, CONSULT 846 That is, the operation control is one of the operation controls specified for this instruction. If it is invalid, then an exception condition is provided, STEP 848. However, if the operation control is valid, then processing continues with the specific operation control that is specified.
[0079] In one example, operation control is a record adapter interrupt operation, which is used to control adapter interrupts. In response to this operation control, the adapter function parameters relevant to adapter interrupts are defined in the device table entry based on the appropriate contents of the function information block.
[0080] An embodiment of the logic associated with this operation is described with reference to figure 9. As an example, the operands for this operation, which are obtained from the function information block, include, for example: an interrupt subclass (ISC); number of interruptions allowed (NOI); an adapter interrupt bit vector offset (AIBVO); a summary (S) notification; an adapter interrupt summary (ABVSO) bit vector offset; an adapter interrupt bit vector address (AIBV); and an adapter interrupt summary (AISB) bit vector address.
[0081] In reference to figure 9, initially, a determination is made as if the number of interruptions (NOIs) specified in the FIB is greater than a model-dependent maximum, CONSULT 900. If so, then an exception condition is provided, STEP 902. However, if the number of interrupts is not greater than the model-dependent maximum, then an additional determination is made as to whether the number of interrupts added to the offset adapter interrupt bit vector (NOI + AIBVO) is greater than a model dependent maximum, CONSULT 904. If so, then an exception condition is provided, STEP 906. If NOI plus AIBVO is not greater than a model dependent maximum, then a determination additional is done as if the AIBV Address plus NOI covers a limit of 4k, CONSULT 908. If it covers the limit of 4k, then an exception condition is provided, STEP 910.
[0082] Otherwise, a determination is made as to whether sufficient resources are available for any necessary resources, STEP 912. If there are not sufficient resources, then an exception condition is provided, STEP 914.
[0083] Otherwise, a determination is made as to whether adapter interruptions are already recorded for this function, STEP 916. In one embodiment, this can be determined by checking one or more of the parameters (for example, in DTE / FTE ). In particular, parameters associated with interrupts, such as NOI, are checked. If the fields are populated, then the adapter is registered for interruptions. If the adapter is already registered, then an exception condition is provided, STEP 918. Otherwise, the interruption parameters are obtained from FIB and placed in the device table entry and optionally in the corresponding function table entry ( FTE) (or other specified location). In addition, an MSI enable indicator is defined in DTE, STEP 920. That is, the PCI function parameters relevant to the adapter interruption are defined in DTE and optionally, in FTE based on the information retrieved from the block. function information. These parameters include, for example, ISC, NOI, AIBVO, S, AIBVSO, AIBV Address and AISB Address.
[0084] In addition to the above, another operation control that can be specified is an unregister adapter interruption operation, an example of which is described with reference to figure 10. With this operation, the function parameters of relevant to the adapter interrupt are reset.
[0085] In reference to figure 10, initially, a determination is made as if the adapter specified by the function identifier is registered for interrupts, CONSULT 1000. If not, then an exception condition is provided, STEP 1002. Otherwise , the interrupt parameters at the function table entry (or other location) and corresponding device table entry are set to zeroes, CONSULT 1004. In one example, these parameters include ISC, NOT, AIBVO, S, AIBSO, Address AIBV and AISB Address.
[0086] As described above, in one embodiment, to obtain information regarding an adapter function, a Call Logic Processor instruction is used. An embodiment of this instruction is shown in figure 11A. As shown, in an example, a Call Logic Processor (PLC) instruction 1100 includes an operation code 1102 indicating that it is the Call Logic Processor instruction; and an indication for a 1104 command. In one example, this indication is an address of a requirement block that describes the command to be performed, and the information in the requirement block is dependent on the command. Examples of requirement blocks and corresponding response blocks for various commands are described with reference to figures 11B-13B.
[0087] Referring initially to figure 11B, a requirement block for a list PCI function command is provided. The list PCI functions command is used to obtain a list of PCI functions that are designated for the requirement configuration (for example, the requisition operating system). A requirement block 1120 includes a number of parameters, such as, for example: Length field 1122: This field indicates the length of the requirement block; Command Code 1124: This field indicates the command of list PCI functions; and Continuation Token 1126: This field is an integer that is used either to initiate a new list PCI function command or to summarize a previous list PCI function command, as described in further detail below.
[0088] When the continuation token field in the command requirement block includes, for example, a value of zero, a new list of PCI functions is requested. When the continuation token field includes, for example, a non-zero value, which was returned from a previous list of PCI functions command, a continuation of a previous list of PCI functions is requested.
[0089] In response to the issuing and processing of the Call Logic Processor instruction for a list PCI function command, a response block is returned. One embodiment of the response block is shown in figure 11C. In an example, an 1150 response block for a list PCI function command includes: Field length 1152: This field indicates the length of the response block; Response Code 1154: This field indicates a status of the command; PCI Function List 1156: This field indicates a list of one or more PCI functions available for the requisition operating system; 1158 continuation token: This field indicates whether a continuation of a previous list of PCI functions is requested. In one example, when the continuation token act in the requirement block and the continuation token act in the response block are zero, all PCI functions assigned to the requirement configuration are represented in the PCI function list; if the continuation token act in the requirement block is zero and the continuation token act in the response block is not zero, additional PCI functions assigned to the requirement configuration may exist that are not represented in the list; if the continuation token act in the requirement block is not zero and the continuation token act in the response block is zero, from the summary point, remaining PCI functions assigned to the requirement configuration are represented in the list; when both the requirement continuation token and response block acts are not zero from the summary point, additional PCI functions assigned to the requirement configuration may exist that have not been represented in any associated PCI function list. The continuation token act remains valid for an indefinite period of time after it is returned, but it may be invalid for a variety of reasons depending on the model, including elapsed system load time; Model 1160 Dependent Data: This field includes data that depends on the system; Number of PCI functions 1162: This field indicates the maximum number of PCI functions supported by the installation; e Entry Size 1164: This field indicates the size of each entry in the PCI function list.
[0090] Additional details regarding the PCI function list are described with reference to figure 11D. In one example, the PCI function list includes a plurality of entries and each entry 1156 includes the following information, as an example: Device ID 1170: This field indicates the I / O adapter associated with the corresponding PCI function; Vendor ID 1172: This field identifies the manufacturer of the I / O adapter associated with the corresponding PCI function; 1174 Function Identifier: This field includes a persistent PCI function identifier; Function identifier 1176: This field identifies the PCI function. Enabling the stored PCI function is a general identifier when a specified bit of the identifier is zero, and it is an enabled identifier when that bit is one. If the PCI function is disabled, a general PCI function enable is stored. If the PCI function is enabled, an enabled PCI function enable is stored. Enabling the PCI function is, in one example, not persistent beyond an IPL, which differs from the PCI function ID, which is persistent and is defined for the life of the I / O configuration setting configuration; and Configuration Status 1178: This field indicates the status of the PCI function. When this indicator is, for example, zero, the state is on hold, and when, for example, one, the state is configured. When on standby, the PCI function enable is the general PCI function enable, and when configured, it is both the general and enabled PCI function enable depending on whether the PCI function is enabled.
[0091] Subsequent to obtaining the list of adapter functions, information can be obtained regarding the attributes of a selected function as designated by a specified PCI function enabling. This information can be obtained by issuing a PLC instruction with a request function command.
[0092] An embodiment of the requirement block for a request PCI function command is described with reference to figure 12A. In an example, order block 1200 includes, for example: Field length 1202: This field indicates the length of the requirement block; Command code 1204: This field indicates the request PCI function command; e Role identifier 1206: This field includes enabling a PCI role (for example, general or enabled) that designates the PCI role to be requested.
[0093] In response to the issuance of the Call Logic Processor instruction for the request PCI function command, a response block is returned. One embodiment of the response block is shown in figure 12B. In an example, a 1250 response block includes the following: Length 1252: This field indicates the length of the response block; Response Code 1254: This field indicates a status of the command; Function Group ID 1256: This field indicates the PCI function group identifier. The PCI role group identifier is used to associate a PCI role group with a set of attributes (also referred to here as characteristics). Each PCI role with the same PCI role group identifier has the same set of attributes; Function ID 1258: a PCI function id is a persistent identifier for the PCI function originally specified by enabling the PCI function and is defined for the life of the I / O configuration definition; Physical Channel Adapter 1260: This value represents a model-dependent identification of the location of the physical I / O adapter that corresponds with the PCI function; Base address records (BARs) 1 ... n 1262: This field includes a plurality of unsigned integers, designated as BARo - BARn, which are associated with the originally specified PCI function, and where the values are also stored in the base address records associated with the PCI function. Each BAR specifies the starting address of a memory space or I / O space within the adapter, and also indicates the type of address space, that is, whether it is a 64 or 32 bit memory space, or a space 32-bit I / O, as examples; Size 1 ... n 1264: This field includes a plurality of unsigned integers, designated as SIZEo - SIZEn. The value of a Size field, when different from zero, represents the size of each address space with each entry corresponding to a BAR previously described. Initial Available DMA 1266: This field includes an address that indicates the beginning of a range of PCI addresses that are available for DMA operations; Final Available DMA 1268: This field includes a value that indicates the end of a range of PCI addresses that are available for DMA operations.
[0094] In addition to obtaining attributes with respect to the specific adapter function, attributes can also be obtained with respect to the group that includes this function. These common attributes can be obtained by issuing a PLC instruction with a request PCI function group command. This command is used to obtain a set of characteristics that are supported for a group of one or more PCI functions designated by the specified PCI function group identifier. The PCI role group identifier is used to associate a PCI role group with the same set of characteristics. An embodiment of a requirement block for the request PCI function group command is described with reference to figure 13A. In an example, order block 1300 includes the following: Field length 1302: This field indicates the length of the requirement block; Command code 1304: This field indicates the request PCI function group command; and role group ID 1306: This field specifies the PCI role group identifier for which attributes are to be obtained.
[0095] And response to the issuing and processing of the Call Logic Processor instruction with a query PCI function group command, a response block is returned. One embodiment of the response block is shown in figure 13B. In an example, a 1350 response block includes: Field length 1352: This field indicates the length of the response block; Response code 1354: This field indicates a status of the command; Number of Interrupts 1356: This field indicates the maximum number of consecutive MSI vector numbers (ie, interrupt event indicators) that are supported by the PCI installation for each PCI function in the specified PCI function group. The possible valid values for the number of interruptions are in the range of zero to 2,048, in one example; Version 1358: This field indicates the version of the PCI specification that is supported by the PCI installation to which the PCI function group designated by the specified PCI group identifier is attached; Frame 1362: This field indicates the frame (or page) sizes supported for the I / O address translation; 1364 Measurement Block Update Interval: This is a value indicating the approximate time interval (for example, in milliseconds) that the PCI function measurement block is updating; DMA 1366 Address Space Mask: This is a value used to indicate which bits in a PCI address are used to identify a DMA address space; e MSI 1368 address: This is a value that is to be used for message signal interruption requirements.
[0096] The function and request list commands described above retrieve information from, for example, the function table. At boot time, or after a warm connection to an adapter, firmware performs a bus walk to determine the adapter's location and determine its basic characteristics. This information is stored by the firmware for the function table entry (FTE) for each adapter. Accessibility for the adapter is determined based on the policy defined by a system administrator and is also defined by firmware for the FTE. The function commands and request list can then retrieve this information and store it in their respective response blocks accessible to the operating system.
[0097] Additionally, the group information is based on a given system I / O infrastructure and the capabilities of the firmware and the I / O hub. This can be stored in FTE or any other convenient location for later retrieval during request processing. In particular, the request group command retrieves the information and stores it in its response block accessible to the operating system.
[0098] Described in detail above is an ability to convert a PCI message signal interrupt to an I / O adapter event notification for an operating system. This provides for a low latency interrupt requirement; a distribution of MSIs from a relatively large number of PCI functions to the operating system; and retaining the variant of the MSI vector designation that fits the MSI for the adapter event notification architecture. Whether it adapts to allow the I / O hub to connect with a relatively large number of PCI functions and eliminates the problem of each writing to an MSI vector that generates a single interrupt.
[0099] In the embodiments described here, the adapters are PCI adapters. PCI, as used here, refers to any adapters implemented according to a PCT-based specification as defined by the Peripheral Component Interconnection Special Interest Group (PCI-SIG) (www.pcisig.com/home), including, but not limited to, PCI or PCIe. In a particular example, Express Peripheral Component Interconnection (PCIe) is a component-level interconnection standard that defines a two-way communication protocol for transactions between I / O adapters and host systems. PCIe communications are encapsulated in packets according to the PCIe standard for transmission over a PCIe bus. Transactions that originate on I / O adapters and end on host systems are referred to as bottom-up transactions. Transactions that originate on host systems and end on I / O adapters are referred to as descendant transactions. The PCIe topology is based on unidirectional point-to-point links that are paired (for example, an uplink, a downlink) to form the PCIe bus. The PCIe standard is maintained and published by PCI-SIG.
[0100] As will be appreciated by one skilled in the art, aspects of the present invention can be incorporated as a computer program system, method or product. Appropriately, aspects of the present invention can take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, microcode, etc.) or an embodiment that combines software and hardware aspects that can all generally referred to here as a "circuit," "module" or "system". In addition, aspects of the present invention may take the form of a computer program product incorporated in one or more computer-readable media having computer-readable program code incorporated therein.
[0101] Any combination of one or more computer-readable media can be used. The computer-readable storage medium may be a computer-readable storage medium. A computer-readable storage medium can be, for example, but is not limited to an electronic storage device, device or system, a magnetic storage device, device or system, an optical storage device, device or system, a device , electromagnetic storage device or system, a semiconductor storage device, device or system, or any suitable combination of the above. More specific examples (a non-exhaustive list) of more specific examples of the computer-readable storage medium include the sequence: a portable floppy disk, a hard disk, a random access memory (RAM), a read-only memory (ROM) ), a programmable erasable read-only memory (EPROM or Flash memory), an optical fiber, a read-only portable compact disc (CD-ROM) memory, an optical storage device, a magnetic storage device, and any appropriate combination of the above. In the context of this document, a computer-readable storage medium can be any tangible medium that can contain or store a program for use by or in conjunction with a device, apparatus or instruction execution system.
[0102] Referring now to Figure 14, in an example, a computer program product 1400 includes, for example, one or more computer readable storage media 1402 for storing computer code readable program code or logic 1404 in the themselves to provide and facilitate one or more aspects of the present invention.
[0103] The program code embedded in a computer-readable medium can be transmitted using an appropriate medium, including, but not limited to, wireless, wired, fiber optic cable, RE, etc., or any suitable combination of the above.
[0104] The computer program code for performing operations for aspects of the present invention can be written in any combination of one or more programming languages, including an object-oriented programming language such as Smalltalk, C ++ or similar, and programming languages. conventional procedure programming, such as the "C" programming language, Assembler or similar programming languages. The program code can run entirely on the user's computer, partially on the user's computer, as a remote software package, partially on the user's computer and partially on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection can be made to a computer (for example, over the Internet using an Internet Service Provider).
[0105] Aspects of the present invention are described here with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by the computer readable program instructions. These computer-readable program instructions can be provided for a general-purpose computer processor, application-specific computer, or other programmable data processing device to produce a machine, such as instructions, which run through the computer's processor or other programmable data processing apparatus, create means to implement the functions / acts specified in the flowchart and / or block or blocks of the block diagram.
[0106] These computer-readable program instructions can also be stored on a computer-readable storage medium that can take a computer, a programmable data processing device, and / or other devices to function in a particular way, such that the computer-readable storage medium having instructions stored therein comprises a manufacturing article including instructions that implement aspects of the function / act specified in the flowchart and / or block or blocks of the block diagram.
[0107] Computer-readable program instructions can also be loaded onto a computer, another programmable data processing device, or another device to cause a series of operational steps to be performed on the computer, another programmable device, or another device to produce a process implemented by a computer, such that the instructions that execute on the computer, another programmable device, or another device implement the functions / acts specified in the flowchart and / or block or blocks of the block diagram.
[0108] The flowchart and block diagrams in the Figures illustrate the architecture, functionality and operation of possible implementations of computer program systems, methods and products in accordance with various embodiments of the present invention. In this sense, each block in the flowchart or block diagrams can represent a module, segment, or portion of instructions, which comprises one or more executable instructions to implement the specified logical functions. In some alternative implementations, the functions observed in the block can occur out of the order observed in the figures. For example, two blocks shown in succession, in fact, can be executed substantially concurrently, or the blocks can sometimes be executed in reverse order, depending on the functionality involved. It will also be noted that each block in the block diagrams and / or flowchart illustration, and combinations of blocks in the block diagrams and / or flowchart illustration, can be implemented by systems based on specific application hardware that perform the specified functions or specified acts or perform combinations of computer instructions and specific application hardware.
[0109] In addition to the above, one or more aspects may be provided, offered, distributed, managed, served, etc. by a service provided that offers the management of consumer environments. For example, the service provider can create, maintain, support, etc. computer code and / or a computer infrastructure that performs one or more aspects for one or more consumers. In return, the service provider may receive payment from a consumer under a subscription and / or fee agreement, as examples. In addition or alternatively, the service provider may receive payment from the sale of advertising content to one or more third parties.
[0110] In one aspect of the present invention, an application can be distributed to carry out one or more aspects of the present invention. As an example, the distribution of an application comprises providing operable computer infrastructure to realize one or more aspects of the present invention.
[0111] As an additional aspect of the present invention, a computing infrastructure can be delivered comprising integrating computer-readable code into a computing system, where the code in combination with the computing system is capable of carrying out one or more aspects of present invention.
[0112] As a further aspect of the present invention, a process for integrating computing infrastructure comprising integrating computer-readable code into a computer system can be provided. The computer system comprises a computer-readable medium, wherein the computer medium comprises one or more embodiments. The code in combination with the computer system is capable of realizing one or more aspects of the present invention.
[0113] Although several embodiments are described above, these are only examples. For example, computing environments of other architectures can incorporate and use one or more aspects of the present invention. Like the examples, servers other than System z® type servers, such as Power Systems servers or other servers offered by International Business Machines Corporation, or servers from other companies may include, use and / or benefit from one or more aspects of the present invention. Additionally, although in the example here, adapters and the PCI hub are considered a part of the server, in other embodiments, they do not necessarily have to be considered a part of the server, but can simply be considered to be coupled with system memory and / or other components of a computational environment. The computing environment does not have to be a server. In addition, although the adapters are PCI based, one or more aspects of the present invention are usable with other adapters or other I / O components. The adapter and the PCI adapter are examples only. In addition, one or more aspects of the present invention are applicable to different interruption schemes than PCI MSI. In addition, although the examples are described in which bits are defined, in other embodiments, bytes or other types of indicators must be defined. In addition, the DTE may include more, less or different information. Many other variations are possible.
[0114] Additionally, other types of computing environments can benefit from one or more aspects of the present invention. As an example, a data processing system suitable for storing and / or executing program code is useful that includes at least two processors coupled directly or indirectly with memory elements via a system bus. The memory elements include, for example, local memory used during the current execution of the program code, physical storage, and cache memory that provide temporary storage of at least some program code in order to reduce the number of times the code must be retrieved from physical storage during execution.
[0115] Input / output or I / O devices (including, but not limited to keyboards, monitors, pointer devices, DASD, tape, CDs, DVDs, flash drives and other memory media, etc.) can be coupled with the system both directly and through intervening I / O controllers. Network adapters can also be coupled with the system to allow the data processing system to be coupled with other data processing systems or remote printers or storage devices over intervening public or private networks. Modems, cable modems, and Ethernet cards are just a few of the available types of network adapters.
[0116] Referring to figure 15, representative components of a host computer system 5000 for implementing one or more aspects of the present invention are depicted. Representative host computer 5000 comprises one or more CPUs 5001 in communication with computer memory (i.e., central storage) 5002, as well as I / O interfaces for 5011 storage medium devices and 5010 networks to communicate with other computers or SANs and the like. The 5001 CPU conforms to an architecture having an architected instruction set and architected functionality. CPU 5001 can have dynamic address translation (DAT) 5003 to transform program addresses (virtual addresses) to actual memory addresses. A DAT typically includes a translation lookaside buffer (TLB) 5007 to temporarily store translations so that subsequent access to computer memory block 5002 does not require the address translation delay. Typically, a cache 5009 is used between computer memory 5002 and processor 5001. Cache 5009 can be hierarchical with a large cache available for more than one CPU and smaller (faster) smaller caches between the large cache and each CPU. In some implementations, lower-level caches are split to provide separate lower-level caches for fetching instruction and data access. In one embodiment, an instruction is fetched from memory 5002 by an instruction search unit 5004 through a 5009 cache. The instruction is decoded into an instruction decoding unit 5006 and dispatched (with other instructions in some embodiments) to instruction execution unit or units 5008. Typically several execution units 5008 are employed, for example, an arithmetic execution unit, a floating point execution unit and a branch instruction execution unit. The instruction is executed by the execution unit, accessing the operands from the specified instruction or memory registers as needed. If an operand is to be accessed (loaded or stored) from memory 5002, a loading / storage unit 5005 typically indicates access under control of the instruction being executed. Instructions can be executed on the hardware circuits or on the internal microcode (firmware) or by a combination of both.
[0117] As noted, a computer system includes information in local (or main) storage, as well as addressing, protection, and reference and recording change. Some aspects of addressing include the format of addresses, the concept of address spaces, the various types of addresses, and the way in which one type of address is translated into another type of address. Part of the main storage permanently includes designated storage locations. The main storage provides the system with directly addressable, fast-access data storage. Both data and programs must be loaded into main storage (from the input devices) before they can be processed.
[0118] The main store can include one or more smaller, quick access temporary stores, sometimes called caches. A cache is typically physically associated with the CPU or an I / O processor. The effects, except on performance, of physical construction and the use of different storage media in general cannot be seen by the program.
[0119] Separate caches can be kept for instructions and data operands. Information within the cache is kept in contiguous bytes in an integral limit called a cache block or cache line (or line, for short). A model can provide an EXTRACT CACHE ATTRIBUTE statement that returns the size of a cache line in bytes. A model can also provide PREFETCH DATA and PREFETCH DATA RELATIVE LONG instructions that perform the previous storage search for the data or instruction cache or the release of data from the cache.
[0120] Storage is observed as a long horizontal bit string. For most operations, accesses to storage proceed in a sequence from left to right. The bit string is subdivided into eight-bit units. A unit of eight bits is called a byte, which is the basic building block of all information formats. Each byte location in the store is identified by a unique non-negative integer, which is the address of that byte location or, simply, the byte address. Adjacent byte locations have consecutive addresses, starting with 0 on the left and proceeding in a sequence from left to right. Addresses are unsigned binary integers and are 24, 31 or 64 bits.
[0121] Information is transmitted between the storage and the CPU or a channel subsystem one byte, or a group of bytes, at a time. Unless otherwise specified, for example, in z / Architecture®, a group of bytes in storage is addressed by the leftmost byte of the group. The number of bytes in the group is either implied or explicitly specified by the operation to be performed. When used in a CPU operation, a group of bytes is called a field. Within each group of bytes, for example, in z / Architecture®, bits are numbered in a sequence from left to right. In z / Architecture®, the leftmost bits are sometimes referred to as the "highest order" bits and the rightmost bits as the "lowest order" bits. Bit numbers are not storage addresses, however. Only bytes can be addressed. To operate on the individual bits of a byte in storage, the entire byte is accessed. The bits in a byte are numbered 0 to 7, from left to right (for example, in z / Architecture®). The bits in an address can be numbered 8-31 or 40-63 for 24 bit addresses, or 1- 31 or 33-63 for 31 bit addresses; they are numbered 0- 63 for 64-bit addresses. Within any other format of fixed length of multiple bytes, the bits that make up the format are numbered consecutively starting from 0. For the purposes of error detection, and preferably for correction, one or more check bits can be transmitted with each byte or with a group of bytes. Such check bits are automatically generated by the machine and cannot be controlled directly by the program. Storage capacities are expressed in the number of bytes. When the length of a storage operand field is implied by an instruction's operation code, the field is said to have a fixed length, which can be one, two, four, eight, or sixteen bytes. Larger fields may be involved for some instructions. When the length of a storage operand field is not implied, but is explicitly stated, the field is said to have a variable length. Operands of variable length can vary in length by one-byte increments (or with some instructions, in multiples of two bytes or other multiples). When information is placed in storage, the contents of only those byte locations are replaced which are included in the designated field, even though the width of the physical path to storage may be greater than the length of the field being stored.
[0122] Certain information units must be at an integral limit on storage. A limit is called an integral for an information unit when its storage address is a multiple of the unit length in bytes. Special names are given for fields of 2, 4, 8 and 16, bytes in an integral limit. A half word is a group of two consecutive bytes at a limit of two bytes and is the basic building block of instructions. A word is a group of four consecutive bytes with a limit of four bytes. A double word is a group of eight consecutive bytes with a limit of eight bytes. A quadruple word is a group of 16 consecutive bytes with a limit of 16 bytes. When storage addresses designate half words, words, double words, and quadruple words, the binary representation of the address contains one, two, three, or four, zero bits to the right, respectively. Instructions must be in full two-byte limits. The storage operands of most instructions do not have limit alignment requirements.
[0123] On devices that implement separate caches for instructions and data operands, a significant delay can occur if the program is stored in a cache line from which the instructions are subsequently fetched, regardless of whether the storage changes the instructions that are subsequently sought.
[0124] In one embodiment, the invention can be practiced by software (sometimes referred to as licensed internal code, firmware, microcode, milicode, pico-code and the like, any of which may be consistent with the present invention). Referring to figure 15, software program code embodying the present invention is typically accessed by processor 5001 from host system 5000 from 5011 long-term storage media devices, such as a CD-ROM drive, drive tape or hard drive. The software program code can be incorporated into any of a variety of known media for use with a data processing system, such as a floppy disk, hard disk, or CD-ROM. The code can be distributed in such a medium, or it can be distributed to users from computer memory 5002 or storage from a computer system over a 5010 network to other computer systems for use by users of such other systems.
[0125] The software program code includes an operating system that controls the function and interaction of various computer components and one or more application programs. Program code is typically paged from the 5011 storage media device to the relatively higher speed computer storage 5002 where it is available to process by the 5001 processor. The techniques and methods for incorporating the software program code into memory, in physical means, and / or distributing software code over networks are well known and will not be further discussed here. Program code, when created and stored on a tangible medium (including, but not limited to, electronic memory (RAM) modules, flash memory, compact discs (CDs), DVDs, magnetic tape and the like is generally referred to as a "product computer program product ". The computer medium program product is typically readable by a processing circuit preferably on a computer system for execution by the processing circuit.
[0126] Figure 16 illustrates a representative workstation or server hardware system on which one or more embodiments can be practiced. The 5020 system of Figure 16 comprises a representative 5021 base computer system, such as a personal computer, a workstation or a server, including optional peripheral devices. The base computer system 5021 includes one or more 5026 processors and a bus employed to connect and allow communication between the 5026 processors and the other components of the 5021 system according to known techniques. The bus connects the 5026 processor with the 5025 memory and 5027 long-term storage that can include a hard disk (including any from a magnetic medium, CD, DVD and flash memory, for example) or a tape drive, for example. The 5021 system must also include a user interface adapter, which connects the 5026 microprocessor across the bus with one or more interface devices, such as a 5024 keyboard, 5023 mouse, 5030 printer / scanner and / or other interface, which can be any user interface device, such as a touch screen, digitized input block, etc. The bus also connects a 5022 display device, such as an LCD screen or monitor, to the 5026 microprocessor via a display adapter.
[0127] The 5021 system can communicate with other computers or computer networks through a network adapter capable of communicating 5028 with a 5029 network. Examples of network adapters are communications channels, token ring, Ethernet or modems. Alternatively, the 5021 system can communicate using a wireless interface, such as a CDPD card (cellular digital packet data). The 5021 system can be associated with such other computers on a local area network (LAN) or a wide area network (WAN), or the 5021 system can be a client in a client / server arrangement with another computer, etc. All of these configurations, as well as the appropriate communications hardware and software, are known in the art.
[0128] Figure 17 illustrates a 5040 data processing network in which one or more embodiments can be practiced. The data processing network 5040 can include a plurality of individual networks, such as a wireless network and a wired network, each of which can include a plurality of individual workstations 5041, 5042, 5043, 5044. Additionally, as those skilled in the art will appreciate, one or more LANs may be included, where the LAN may comprise a plurality of intelligent workstations coupled with a host processor.
[0129] Still referring to figure 17, networks can also include computers or mainframe servers, such as a gateway computer (5046 client server) or application server (remote 5048 server that can access a data repository and can also be accessed directly from a 5045 workstation). A 5046 gateway computer serves as an entry point for each individual network. A gateway is required when connecting one network protocol to another. The gateway 5046 can preferably be coupled to another network (the Internet 5047, for example) via a communications link. The 5046 gateway can also be coupled directly to one or more 5041, 5042, 5043, 5044 workstations using a communications link. The gateway computer can be deployed using an IBM eServer z System® server available from International Business Machines Corporation.
[0130] Referring concurrently to figure 16 and figure 17, software programming code 5031 that can incorporate one or more aspects can be accessed by the 5026 processor of the 5020 system from the long-term storage media 5027, such as a drive CD-ROM or hard disk. The software programming code can be incorporated into any of a variety of known media for use with a data processing system, such as a floppy disk, hard disk, or CD-ROM. The code can be distributed in such a medium, or it can be distributed to 5050, 5051 users from the memory or storage of one computer system over a network to other computer systems for use by users of such other systems.
[0131] Alternatively, the programming code can be incorporated into the 5025 memory, and accessed by the 5026 processor using the processor bus. Such programming code includes an operating system that controls the function and interaction of the various computer components and one or more 5032 application programs. Program code is normally paged from the 5027 storage medium for 5025 high speed memory where it is available to process by the 5026 processor. The techniques and methods for incorporating software programming code into memory, in the physical environment, and / or distributing software code over networks are well known and will not be further discussed here. Program code, when created and stored on a tangible medium (including, but not limited to, electronic memory modules (RAM), flash memory, compact discs (CDs), DVDs, magnetic tape and the like is generally referred to as a "product computer program product ". The computer medium program product is typically readable by a processing circuit preferably on a computer system for execution by the processing circuit.
[0132] The cache that is most readily available to the processor (usually faster and smaller than other processor caches) is the smallest cache (LI or level one) and main storage (main memory) is the most level cache high (L3 if there are 3 levels). The lowest level cache is generally divided into an instruction cache (I-Cache) that holds instructions for the machine to be executed and a data cache (D-Cache) that holds data operands.
[0133] Referring to figure 18, an example processor embodiment is represented for the 5026 processor. Typically one or more 5053 cache levels are employed to temporarily store blocks of memory in order to improve the performance of the processor. The 5053 cache is a high-speed buffer that holds cache lines of memory data that are likely to be used. Typical cache lines are 64, 128 or 256 bytes of memory data. Separate caches are generally employed to cache instructions instead of caching data. Cache coherence (synchronization of copies of lines in memory and caches) is generally provided by several "snoop" algorithms well known in the art. 5025 main memory storage for a processor system is generally referred to as a cache. In a processor system having 4 cache levels 5053, main storage 5025 is sometimes referred to as the level 5 (L5) cache as it is typically faster and only retains a portion of the non-volatile storage (DASD, tape, etc.) that is available for a computer system. The main storage 5025 "caches" pages of data paged in and out of the main storage 5025 by the operating system.
[0134] A program counter (instruction counter) 5061 keeps track of the address of the current instruction to be executed. A program counter on the z / Architecture® processor is 64 bits and can be truncated to 31 or 24 bits to support the previous addressing limits. A program counter is typically incorporated into a computer's PSW (program status word) such that it persists during context switching. Thus, a program in progress, having a program counter value, can be interrupted, for example, by the operating system (switching context from the environment program to the environment operating system). The program's PSW maintains the program counter value while the program is not active, and the operating system's program counter (on the PSW) is used while the operating system is running. Typically, the program counter is incremented by an amount equal to the number of bytes in the current instruction. RISC (Reduced Instruction Set Computing) instructions typically have a fixed length while CISC (Complex Instruction Set Computing) instructions are typically of variable length. IBM z / Architecture® instructions are CISC instructions having a length of 2, 4 or 6 bytes. The program counter 5061 is modified either by the context switching operation or an operation taken by branching a branching instruction for example. In the context switching operation, the current program counter value is saved in the program status word along with other status information about the program being executed (such as condition codes), and a new program counter value is saved. loaded pointing to an instruction for a new program module to be executed. An operation taken by branch is performed in order to allow the program to make decisions or cycle within the program by loading the result of the branch instruction to the program counter 5061.
[0135] Typically a 5055 instruction search unit is used to search for instructions on behalf of the 5026 processor. The search unit either searches for "next sequential instructions", instructions targeted by instructions taken by branch, or first instructions in a program that follows context switching. Modern Instruction search units generally employ pre-search techniques to pre-speculatively search for instructions based on the propensity that pre-searched instructions should be used. For example, a search unit can fetch 16 instruction bytes which includes the additional bytes and the next sequential instruction for additional sequential instructions.
[0136] The searched instructions are then executed by the 5026 processor. In one embodiment, the searched instructions are passed to a 5056 sending unit of the search unit. The sending unit decodes the instructions and directs information about the decoded instructions to appropriate units 5057, 5058, 5060. A 5057 execution unit will typically receive information about decoded arithmetic instructions from the instruction search unit 5055 and will perform arithmetic operations in operands according to the instruction's op code. Operands are provided for execution unit 5057 preferably either from memory 5025, archived records 5059 or from an immediate field of the instruction being executed. Execution results, when stored, are stored both in 5025 memory and in 5059 records on other machine hardware (such as control registers, PSW registers and the like).
[0137] A 5026 processor typically has one or more 5057, 5058, 5060 units to perform the instruction function. Referring to figure 19A, an execution unit 5057 can communicate with general architected registers 5059, a send / decode unit 5056, a load / storage unit 5060, and another 5065 processor units via 5071 interface logic. An execution unit 5057 can employ several register circuits 5067, 5068, 5069 to retain information that the arithmetic logic unit (ALU) 5066 will operate on. ALU performs arithmetic operations such as addition, subtraction, multiplication and division as well as a logical function such as AND, OR and OU-Exclusive (XOR), rotate and move. Preferably ALU supports specialized operations that are dependent on the project. Other circuits can provide other 5072 architecture installations including condition codes and retrieve support logic for example. Typically the result of an ALU operation is maintained in a 5070 checkout circuit that can direct the result to a variety of other processing functions. There are many arrangements of processor units, the present description is intended only to provide a representative understanding of a preferred embodiment of the present invention.
[0138] An ADD instruction for example, can be executed in a 5057 execution unit having arithmetic and logic functionality while a floating point instruction for example, can be executed in a floating point execution having specialized floating point capability. Preferably, an execution unit operates on the operands identified by an instruction performing a function defined by operation code on the operands. For example, an ADD instruction can be executed by a 5057 execution unit on the operands found in two 5059 registers identified by the instruction record fields.
[0139] The execution unit 5057 performs the arithmetic addition in the two operands and stores the result in a third operand where the third operand can be a third record or one of the two source records. The execution unit preferably uses a 5066 Arithmetic Logic Unit (ALU) which is capable of performing a variety of logic functions such as Displacement, Rotation, AND, OR and O- exclusive as well as a variety of algebraic functions including any addition, subtraction, multiplication, division. Some 5066 ALUs are designed for scalar operations and some for floating point. Data can be Big Endian (where the least significant byte is in the highest byte address) or Little Endian (where the least significant byte is in the lowest byte address) depending on the architecture. IBM's Z Architecture is Big Endian. Signaled fields can be in sign and magnitude, complement of 1 or complement of 2 depending on the architecture. A complement number of 2 is advantageous in that the ALU does not need to design a subtraction capability since either a negative value or a positive value in the complement of 2 only needs an addition within the ALU. Numbers are commonly described beforehand, where a 12-bit field defines an address in a 4,096-byte block and is commonly described as a 4-Kbyte (Kilobytes) block, for example.
[0140] Referring to figure 19B, branch instruction information for executing a branch instruction is typically sent to a 5058 branch unit that generally employs a branch prediction algorithm such as a 5082 branch historical table to predict the outcome branch before other conditional operations are complete. The target of the current branch instruction will be sought and speculatively executed before the conditional operations are complete. When conditional operations are completed the speculatively executed branching instructions are either completed or discarded based on the conditions of the conditional operation and the speculated result. A typical branching instruction can test condition and branching codes for a destination address if the condition codes satisfy the branching requirement of the branching instruction, a destination address can be calculated based on the various numbers including those found in the fields of record or an immediate instruction field for example. The 5058 branch unit can employ an ALU 5074 having a plurality of 5075, 5076, 5077 input register circuits and an 5080 output register circuit. The 5058 branch unit can communicate with general registers 5059, send / decode unit 5056 or other 5073 circuits, for example.
[0141] The execution of a group of instructions can be interrupted for a variety of reasons including context switching initiated by an operating system, a program exception or error causing context switching, an I / O interrupt signal causing the switching of context or multiple threading activity from a plurality of programs (in a multi-threaded environment), for example. Preferably the context switching action saves status information about a running program and then loads status information about another program being invoked. Status information can be saved in hardware registers or in memory for example. Status information preferably comprises a program counter value pointing to the next instruction to be executed, condition codes, memory translation information and archived record content. The context switching activity can be exercised by hardware circuits, application programs, operating system programs or firmware code (microcode, picocode or licensed internal code (LIC)) alone or in combination.
[0142] A processor accesses operands according to methods defined by the instruction. The instruction can provide an immediate operand using the value of a portion of the instruction, it can provide one or more record fields explicitly pointing to both general purpose records and special purpose records (floating point records for example). The instruction can use implicit records identified by an op code field as operands. The instruction can use memory locations for the operands. An operand's memory location can be provided by a record, an immediate field, or a combination of records and immediate field as exemplified by a z / Architecture® long-displacement installation where the instruction defines a base record, a index record and an immediate field (displacement field) that are added together to provide the operand address in memory for example. The location here typically implies a location in main memory (main storage) unless otherwise noted.
[0143] Referring to figure 19C, a processor accesses storage using a 5060 loading / storage unit. The 5060 loading / storage unit can perform a loading operation by obtaining the address of the target operand in memory 5053 and loading the operand in a 5059 register or other 5053 memory location, or it can perform a storage operation by obtaining the address of the target operand in memory 5053 and store data obtained from a 5059 register or another 5053 memory location in the location of target operand in memory 5053 The 5060 loading / storage unit can be speculative and can access memory in a sequence that is out of order with respect to the instruction sequence, however the 5060 loading / storage unit is to maintain the appearance for programs where the instructions were executed in order. A 5060 loading / storage unit can communicate 5084 with general 5059 registers, 5056 sending / decoding unit, 5053 cache / memory interface or other 5083 elements and comprises several 5086, 5087, 5088 and 5089 register circuits, 5085 ALUs and logic 5090 control panel to calculate storage addresses and to provide online sequencing to keep operations in order. Some operations may be out of order, but the loading / storage unit provides functionality to make operations out of order appear to the program as having been carried out in order, as is well known in the art.
[0144] Preferably addresses that an application program "sees" are often referred to as virtual addresses. Virtual addresses are sometimes referred to as "logical addresses" and "effective addresses". These virtual addresses are virtual in that they are redirected to physical memory locations by one of a variety of dynamic address translation (DAT) technologies including, but not limited to, simply prefixing a virtual address with an offset value, translate the virtual address through one or more translation tables, the translation tables preferably comprising at least one segment table and one page table alone or in combination, preferably the segment table having an entry that points to the translation table page. In Architecture Z, a translation hierarchy is provided including a first region table, a second region table, a third region table, a segment table and an optional page table. The performance of address translation is generally improved using a translation lookaside buffer (TLB) that comprises entries that map a virtual address to an associated physical memory location. Entries are created when the DAT translates a virtual address using the translation tables. Subsequent to the use of the virtual address you can then use the fast TLB entry instead of the slow sequential translation table accesses. TLB content can be managed by a variety of replacement algorithms including LRU (Less Recently Used).
[0145] In the case where the processor is a processor of a system of multiple processors, each processor has responsibility for maintaining divided resources, such as I / O, caches, TLBs and memory, interlocked for consistency. Typically, "snoop" technologies will be used to maintain cache coherence. In a snoop environment, each cache line can be marked as being in either a split state, a unique state, an altered state, an invalid state and the like in order to facilitate division.
[0146] The 5054 I / O units (figure 18) provide the processor with means for attachment with peripheral devices including tape, disk, printers, monitors, and networks for example. I / O units are usually presented to the computer program by software drivers. In mainframes, such as the z System from IBM®, channel adapters and open system adapters are mainframe I / O units that provide communications between the operating system and peripheral devices.
[0147] Additionally, other types of computing environments can benefit from one or more aspects. As an example, an environment can include an emulator (for example, software or other emulation mechanisms), in which a particular architecture (including, for example, instruction execution, archived functions, such as address translation, and archived records) or a subset of them is emulated (for example, on a native computer system having a processor and memory). In such an environment, one or more emulation functions of the emulator may implement one or more embodiments, even though a computer running the emulator may have a different architecture than the capabilities being emulated. As an example, in emulation mode, the specific operation or instruction being emulated is decoded, and an appropriate emulation function is built in to implement the individual operation or instruction.
[0148] In an emulation environment, a host computer includes, for example, memory to store instructions and data; an instruction fetch unit to fetch instructions from memory and optionally to provide local temporary storage for the fetch instruction; an instruction decoding unit to receive the instructions sought and to determine the type of instructions that must be sought; and an execution unit instruction to execute the instructions. The run can include load data for a record from memory; storing data back into memory from a record; or performing some kind of logical or arithmetic operation, as determined by the decoding unit. In one example, each unit is implemented in software. For example, the operations being performed by the units are implemented as one or more subroutines within emulator software.
[0149] More particularly, on a mainframe, engineered machine instructions are used by programmers, commonly "C" programmers today, usually through a compiler application. These instructions stored on the storage medium can be executed natively on the IBM® Z Architecture Server, or alternatively on machines running other architectures. They can be emulated on existing servers and in future IBM® mainframe servers and on other IBM® machines (for example, Power Systems servers and System Servers x). They can run on machines that run Linux on a wide variety of machines using hardware manufactured by IBM®, Intel®, AMD, and others. In addition to running that hardware under Z Architecture, Linux can be used as well as machines that use Hercules, UMX or ESI (Fundamental Software, Inc.) emulation, where in general the execution is in an emulation mode. In emulation mode, the emulation software is run by a native processor to emulate the architecture of an emulated processor.
[0150] The native processor typically runs emulation software comprising both firmware and a native operating system to perform emulation of the emulated processor. The emulation software is responsible for fetching and executing instructions from the emulated processor architecture. The emulation software maintains an emulated program counter to keep track of instruction limits. The emulation software can retrieve one or more emulated machine instructions at a time and convert the one or more emulated machine instructions to a corresponding group of native machine instructions for execution by the native processor. These converted instructions can be cached so that faster conversion can be achieved. Nevertheless, the emulation software is to maintain the architectural rules of the emulated processor architecture in order to ensure that the operating systems and applications written for the emulated processor operate correctly. In addition, the emulation software is to provide features identified by the emulated processor architecture including, but not limited to, control registers, general purpose registers, floating point registers, dynamic address translation function including segment tables and index tables. page, for example, interrupt mechanisms, context switching mechanisms, Time of Day (TOD) clocks and interfaces designed for I / O subsystems such that an operating system or an application program designed to run on the emulated processor, can run on the native processor using the emulation software.
[0151] A specific instruction being emulated is decoded, and a subroutine is called to perform the function of the individual instruction. An emulation software function that emulates an emulated processor function is implemented, for example, in a "C" driver or subroutine, or some other method of providing a driver for specific hardware as will be within the expertise of those experts in the after understanding the description of the preferred embodiment. Several software and hardware emulation patents including, but not limited to, U.S. Patent No. 5,551,013, entitled "Multiprocessor for Hardware Emulation", by Beausoleil et al; and U.S. Patent Letter No. 6,009,261, entitled "Preprocessing of Stored Target Routines to emulate Incompatible Instructions on a Target Processor", by Scalzi et al; and U.S. Patent Letter No. 5,574,873, entitled "Decoding Guest Instruction to Directly Access Emulation Routines emulating the Guest Instructions", by Davidian et al; and U.S. Patent Letter No. 6,308,255, entitled "Symmetrical Multiprocessing Bus and Chipset Used for Coprocessor Support Allowing Non-Native Code to Run in a System", by Gorishek et al; and U.S. Patent Letter No. 6,463,582, entitled "Dynamic Optimizing Object Code Translator for Architecture Emulation and Dynamic Optimizing Object Code Translation Method", by Lethin et al; and U.S. Patent Letter No. 5,790,825, entitled "Method to emulate Guest Instructions on a host computer Through Dynamic Recompilation of Host Instructions" by Eric Traut; and many others, illustrate a variety of known ways to achieve the emulation of an instruction format designed for a different machine for a target machine available to the person skilled in the art.
[0152] In figure 20, an example of a 5092 emulated host computer system is provided that emulates a host computer system 5000'of a host architecture. In the 5092 emulated host computer system, the 5091 host processor (CPU) is an emulated host processor (or virtual host processor) and comprises a 5093 emulation processor having a different native instruction configuration architecture than that of the processor 5091 from host computer 5000 '. The emulated host computer system 5092 has memory 5094 accessible to the emulation processor 5093. In the example embodiment, memory 5094 is partitioned into a portion of host computer memory 5096 and a portion of emulation routines 5097. The memory of 5096 host computer is available for 5092 emulated host computer programs according to host computer architecture. The 5093 emulation processor executes native instructions from an architectural instruction set of a different architecture than that of the 5091 emulated processor, the native instructions obtained from the 5097 emulation routine memory, and can access a host instruction for execution from a program in host computer memory 5096 employing one or more instructions obtained in an access / decoding sequence and routine that can decode the host instructions accessed to determine a native instruction execution routine to emulate the instruction function host name accessed. Other facilities that are defined for the host computer system architecture 5000 'can be emulated by the routines of architected facilities, including such facilities as general purpose records, control records, dynamic address translation and I / O subsystem support and processor cache, for example. Emulation routines can also take advantage of functions available on the 5093 emulation processor (such as general registration and dynamic translation of virtual addresses) to improve the performance of emulation routines. Special hardware and unloading mechanisms can also be provided to assist the 5093 processor in emulating the host computer's 5000 'function.
[0153] The terminology used here is for the purpose of describing particular embodiments only and is not intended to be limiting. As used here, the singular forms "one", "one", "a" and "o" are also intended to include plural forms, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of declared features, members, steps, operations, elements, and / or components, but do not prevent the presence or addition of one or more other functionalities, members, stages, operations, elements, components and / or groups thereof.
[0154] The corresponding structures, materials, acts, and equivalents of all means or stages plus function elements in the claims below, if any, are intended to include any structure, material, or act to perform the function in combination with others elements claimed as specifically claimed. The description of one or more embodiments has been presented for the purposes of illustration and description, but is not intended to be exhaustive or limited in the form disclosed. Many modifications and variations will be apparent to those skilled in the art. The embodiment has been chosen and described in order to better explain various aspects and practical application, and to allow other experts in the art to understand various embodiments with various modifications as are suitable for the particular intended use.

权利要求:
Claims (10)
[0001]
1. Method of managing interruption requests in a computational environment, the method characterized by the fact that it comprises: based on the execution of an interruption operation of an MPFC instruction (Modify PCI Function Controls) that specifies a function identifier of an adapter, specifying a location in the system memory of an adapter interrupt bit vector (AIBV) for the adapter, the AIBV included in an array of one or more AIBVs, and a location in the system memory of a summary bit for interrupt adapter (AISB) from an AISB array; receive an interrupt request from the adapter; and based on the request received, configure, through an input / output (I / O) hub coupled to the adapter, an indicator in the AIBV indicating a type of adapter event and configuring the AISB indicating that an indicator is defined in the AIBV, in that the configuration of the indicator in the AIBV comprises: determining whether a vector number provided in the request is within the number of interruptions allowed for the adapter; and based on the determination of the vector number is within the allowed number of interruptions, use the vector number, an AIBV offset and an AIBV address to determine the indicator in the AIBV to be defined.
[0002]
2. Method, according to claim 1, characterized by the fact that it also comprises presenting an interruption to an operating system, the interruption based on the interruption request.
[0003]
3. Method, according to claim 2, characterized by the fact that the interrupt request represents a plurality of interruptions signaled by message and the interruption in the operating system is part of an event notification from the input / output adapter to the system operational.
[0004]
4. Method, according to claim 2, characterized by the fact that it also includes obtaining, based on the presentation, one or more indications of AIBV for one or more adapters, specifying at least one reason for interruption per adapter.
[0005]
5. Method, according to claim 4, characterized by the fact that it also comprises obtaining a plurality of indications of AIBV, specifying a plurality of reasons for interruption, the plurality of reasons for interruption corresponding to the plurality of interruption requests.
[0006]
6. Method, according to claim 5, characterized by the fact that obtaining comprises the use of AISB in obtaining one or more indications of AIBV in one or more AIBVs.
[0007]
7. Method, according to claim 1, characterized by the fact that the configuration of the indicator in the AIBV comprises: using an adapter request identifier to obtain a device table entry, the device table entry comprising a value that specifies the number of interrupts allowed for the adapter; and based on the determination of the vector number is within the permitted number of interrupts, using one or more parameters from the device table entry to locate an AIBV start position.
[0008]
8. Method according to claim 1, characterized by the fact that the AIBV for the adapter comprises a plurality of indicators for the adapter, the plurality of indicators indicating a plurality of types of events associated with the adapter.
[0009]
9. Method, according to claim 1, characterized by the fact that the matrix of one or more AIBVs includes another AIBV for another adapter and in which a number of indicators in the AIBV for the adapter is different from the number of indicators in the other AIBV to the other adapter.
[0010]
10. Method, according to claim 1, characterized by the fact that the function identifier includes an enabling indicator that indicates whether the identifier is activated, a number that identifies the adapter and an instance number to indicate a specific instance of the identifier.

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CN102906722B|2015-07-08|

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AU2010355798A1|2012-12-20|

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JP5719435B2|2015-05-20|

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WO2011160707A1|2011-12-29|

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EP2430558B1|2015-03-25|

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PT2430558E|2015-05-20|

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CN102906722A|2013-01-30|

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SG186080A1|2013-01-30|

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ZA201209699B|2015-06-24|

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RU2012147704A|2014-05-20|

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法律状态:
2019-01-08| B06F| Objections, documents and/or translations needed after an examination request according [chapter 6.6 patent gazette]|

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2019-08-13| B06U| Preliminary requirement: requests with searches performed by other patent offices: procedure suspended [chapter 6.21 patent gazette]|

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2020-06-02| B09A| Decision: intention to grant [chapter 9.1 patent gazette]|

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2020-11-03| B16A| Patent or certificate of addition of invention granted [chapter 16.1 patent gazette]|Free format text: PRAZO DE VALIDADE: 20 (VINTE) ANOS CONTADOS A PARTIR DE 08/11/2010, OBSERVADAS AS CONDICOES LEGAIS. |

优先权:

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申请号 | 申请日 | 专利标题

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US12/821,175|2010-06-23|

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US12/821,175|US8572635B2|2010-06-23|2010-06-23|Converting a message signaled interruption into an I/O adapter event notification|

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PCT/EP2010/067023|WO2011160707A1|2010-06-23|2010-11-08|Converting a message signaled interruption into an i/o adapter event notification|

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